Integrated circuit testing methods using well bias modification

ABSTRACT

Methods for testing a semiconductor circuit ( 10 ) including testing the circuit and modifying a well bias ( 14, 18 ) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control ( 40 ) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

TECHNICAL FIELD

The present invention relates generally to integrated circuit testing.

BACKGROUND ART

A goal of integrated circuit (IC) testing is to distinguish defect-freedevices from those that have defects. Many commonly occurring defects,however, are difficult to detect and characterize during traditionaltesting. In particular, there are a number of defects that are difficultto test during voltage-based testing, static leakage current (“IDDQ”)testing, and stress-related testing.

Relative to voltage-based testing, testing under nominal well-biasconditions does not always detect defects. For instance, voltage-basedtesting at nominal well-bias conditions may be completed using a low-Vddtest to aid in detection of defects. However, not all defects arereadily apparent using such tests.

Relative to IDDQ testing, increased background currents make itdifficult to distinguish between defect-related IDDQ, i.e., thoseusually manifested in an elevated IDDQ, from normal defect-free chipbackground current. One proposed solution to this problem is touniformly modify the well and/or substrate biases so that the thresholdvoltages of all of the transistors are increased in order to decreaseleakage current and make defect-related IDDQ discernable. However, thissolution overlooks the relationships between IDDQ and substrate biasthat may be leveraged to detect defects. Another proposed solution isIDDQ versus Vdd characterization. Unfortunately, defects are stilldifficult to discern and characterize based on this comparison.

Relative to stress-related testing, latent defects may exist inmanufactured ICs that are initially benign and therefore not detectableat wafer or package level test. However, degradation during use cancause the circuit to fail before the end of its specified life.Accelerated life stress tests are used to detect such defect-related“reliability fails” so that defect-laden ICs are not shipped to thecustomer. Today, elevated voltage stress tests and elevatedtemperature/voltage burn-in tests are used as accelerated life stresses.One of the reasons for burning in chips at high voltage and temperature,or voltage stressing chips at high voltage, is to create large currents.Such currents are especially useful for opening up resistive-open-typedefects. Another reason for generating high currents is to increasepower dissipation, which generates heat and, in turn, mechanicalstresses. These mechanical stresses are also especially useful foropening up resistive-open-type defects. Unfortunately, both types oftests are becoming increasingly difficult to apply. First, voltagestress is problematic relative to near-future technologies becauseplacing a large electric field across the gate oxide has increasinglyforced the chips into gate oxide failure prematurely. Second, burn-in isalso becoming less desirable as power, especially static power, exceedsequipment delivery capabilities. Also, both traditional stress methodsdisadvantageously require compromises in design to ensure circuitfunctionality under the applied stresses.

In view of the foregoing, there is a need for IC testing methods thatprovide higher resolution voltage-based and IDDQ testing and moreefficient, less damaging stress testing.

DISCLOSURE OF THE INVENTION

The invention relates to integrated circuit testing. The inventionprovides methods for testing a semiconductor circuit including testingthe circuit and modifying well biases during testing. The methodsimprove the resolution of voltage-based and IDDQ testing and diagnosisby modifying well biases during test. In addition, the methods providemore efficient, less damaging stresses during stress testing. Themethods apply to ICs where the semiconductor bulk nodes (wells and/orsubstrates) are wired separately from the chip power Vdd and ground GND,allowing for external control of the bulk potentials during test. Ingeneral, the methods rely on using the bulk bias to change transistorthreshold voltages or place a larger electric field across the gateoxide.

Relative to voltage-based testing, the methods allow standard voltagetesting techniques to be used, but provide improved detectability anddiagnosability of manufacturing flaws versus tests done under a nominalwell-bias condition. Relative to IDDQ testing, independent bulk biasmodification takes advantage of the relationship between bulk bias andIDDQ, allows characterization of multiple independent relationships bymodifying n-transistor voltage thresholds (Vtn) and p-transistor voltagethresholds (Vtp) separately, allows a wider range of IDDQ withoutdamaging the device with large electric fields across the oxide, and theincreased ability to induce jumps in IDDQ due to degraded logic levelsexceeding lowered transistor thresholds or falling below increasedtransistor thresholds.

With regard to stress testing, the methods allow for generation of largecurrents for stressing a chip without application of a high and damagingelectric field across the gate oxide and without necessarily relying onhigh temperature, i.e., without necessarily requiring a burn-in oven. Inaddition, because the transistor threshold voltage (Vt) has a strongeffect on both switching and static currents, the methods allow tuningthe well biases during stress to achieve the desired mix of static andswitching currents. Accordingly, it provides a method for improvedcircuit stress compared to standard voltage stress and burn-in stresstechniques. In addition, the methods also help circuits function atstress conditions and allows for localizing and diagnosing defects. Themethods can be used to “bump” gate oxide stress and tailor well bias ona chip-by-chip basis during burn-in.

The foregoing and other features of the invention will be apparent fromthe following more particular description of embodiments of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of this invention will be described in detail, withreference to the following figures, wherein like designations denotelike elements, and wherein:

FIG. 1 shows an integrated circuit for testing and a testing systemaccording to an embodiment of the invention.

FIG. 2 shows an integrated circuit for testing including wellpartitions.

FIG. 3 shows a graph for detecting defects during IDDQ testing accordingto an embodiment of the invention.

FIG. 4 shows a prior art graph illustrating the difficulties ofdetecting defects during IDDQ versus Vdd testing.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

With reference to the accompanying drawings, FIG. 1 shows an integratedcircuit (IC) 10 including semiconductor bulk nodes 12 that are wiredseparately from the chip power voltage (VDD) and ground (GND), whichallows for external control of the bulk bias during test. The methodsinclude testing a circuit 10 including independently modifying a p-well14 bias of an n-transistor 16 and an n-well 18 bias of a p-transistor20; and determining whether a defect exists from the testing. As usedherein, the term “bulk” or, equivalently, “bulk node,” shall refer toboth wells and substrates. Similarly, based on the fact that moderndigital complementary metal-oxide semiconductor (CMOS) processes rarelyuse the configuration of a single well and a substrate (i.e., thetransistor bulk node is nearly always a well), the term “well” refers toboth wells and substrates. Accordingly, “p-bulk” and “p-well” shallcollectively refer to p-wells and p-substrates, and “n-bulk” and“n-well” shall collectively refer to n-wells and n-substrates.Transistor threshold voltages collectively will be denoted “Vt,” andwill be independently denoted as “Vtn” for the n-transistor and “Vtp”for the p-transistor. As used herein, “nominal bias conditions” refersto a standard operational value including ground (GND) for p-well 14 andVdd for n-well 18.

A modification of the well bias controls transistor Vt during thetesting. In particular, increased Vtn is generated by decreasing thep-bulk bias from a nominal value; decreased Vtn is generated byincreasing p-bulk bias from a nominal value; increased Vtp is generatedby increasing the n-bulk bias from a nominal value; and decreased Vtp isgenerated by decreasing n-bulk bias from a nominal value. Decreasing Vtstrengthens the transistor, and increasing Vt weakens the transistor.

The testing may include voltage-based testing, static leakage currentIDDQ testing, and stress testing. Each type of testing will be describedseparately relative to a number of applications and related examples. Itshould be recognized, however, that the methods should not be limited tothe particular testing described or the particular applications andexamples other than as provided in the attached claims.

With continuing reference to FIG. 1, a testing system 30 for IC 10 isalso shown. Testing system 30 includes a power supply 32 that has chipground (GND) coupled to the n-transistor's source terminal 34 and VDDcoupled to the p-transistor's source terminal 36. In addition, testingsystem 30 includes a control unit 40 having a tester 60 for testing IC10 and a defect determinator 62 for determining whether a defect existsbased on the testing. Control unit 40 controls a well bias ofn-transistor 16 via a coupling 42 to its p-well 14, and a well bias ofp-transistor 20 via a coupling 44 to its n-well 18. Control unit 40 mayalso control power supply 32. In addition, control unit 40 isprogrammable to determine defects based on the testing. Although notshown for clarity, as known to those skilled in the art, IC 10 may bepositioned in a burn-in oven for stress testing as will be describedbelow. In addition, it should be recognized that while FIG. 1 onlyillustrates a twin-well embodiment, the teachings of the invention areextendable to use for a single well or to more than two wells. As shownin FIG. 2, wells 14, 18 can be partitioned into p-wells 14A, 14B andn-wells 18A, 18B, and each partition may be coupled to control unit 40for separate testing according to the methods described below. Althoughone partition of each well is shown, it should be understood that anynumber of partitions may be provided. It should be recognized that FIGS.1 and 2 are greatly simplified. For example, input protection circuitry,the multitudes of other transistors, some chip internal wiring, etc.,are not shown for clarity purposes.

As will be illustrated in the Applications/Examples that follow, thedetermining step according to the methods may include comparing outputsof the circuit to expected results for a defect-free circuit, which maybe stored in control unit 40. Alternatively, the determining step mayuse the circuit as its own reference. That is, comparing the circuit'soutput for a certain test to a reference output of the same circuitunder different well bias conditions. Defect detection can be determinedbased on theoretical predictions and/or empirical data.

Testing may take a variety of general forms. In one embodiment, testingmay include modifying the well biases to one of a plurality of extremeconditions, e.g., minimum n-well bias and maximum p-well bias, ormaximum n-well bias and minimum p-well bias or other permutations. Interms of this testing, the determining step may observe the well-biasextreme conditions in isolation. Alternatively, during the extremecondition testing, the determining step may include observing a circuitparameter in addition to well bias during the testing. A “circuitparameter” may be any circuit function that may be observed duringtesting such as chip speed as measured by ring oscillator frequency,chip speed as measured by scan chain flush delay, minimum VDD where thechip operates to specifications, maximum VDD where the chip operates tospecifications, static leakage current, average dynamic powerconsumption, etc. In addition, “circuit parameters” may also includequantities that can be controlled during test including, for example,VDD, temperature and clock speed. Testing may also include modificationof at least one of the circuit parameters, e.g., chip speed, Vdd,temperature, etc. In any case, the determining step may includecomparing results to expected results at extreme conditions.

With special regard to when partitions are provided (FIG. 2), themodifying step may include applying a different well bias condition toat least one partition 14A compared to, at least one other partition14B, and the determining step may be applied to IC 10 as a whole or on apartition-by-partition basis. Alternatively, the modifying step mayinclude applying a plurality of different well bias conditions to aplurality of different partitions 14A, 14B, 18A, 18B, and thedetermining step may include comparing the results of the testing to oneanother to localize a defect.

The description includes the following headers for clarity purposesonly: I. Voltage-based Testing, II. IDDQ Testing; m. Stress Testing; andIV. Miscellany.

I. Voltage-Based Testing

Voltage-based testing using the invention includes implementing nowknown or later developed techniques for such testing with modificationof well bias. For example, conventional voltage-based testing mayinclude applying a test vector by, for example, stimulating IC 10through primary or scan chain inputs 64, 66 (FIG. 1). A “test vector”may be, for example, binary data generated by well-known automatic testpattern generation software. Conventional voltage-based testingcontinues by propagating the effects to logically observable points(e.g., primary outputs 70, 72 or scan chain latches 64, 66) andcomparing the results to an expected outcome. The method of modifyingthe well bias during test (e.g., during the application of the testvector and propagation to logically observable points), however,enhances the detectability and diagnosability of manufacturing defects.For example, a higher threshold voltage Vt for the transistors makes thetransistors weaker, i.e., gives them a higher equivalent resistance. Inthis case, a short (defect) resistance, for example, remains constant,so the short looks more severe and is more easily detected. Voltagetesting at a low-Vdd similarly enhances defect detection by weakeningtransistors, but this test provides neither strengthening transistors toenhance detection nor strengthening or weakening the n-transistor orp-transistor independently of one another. There are some unique defectsthat testing with independently modified well bias can detect thatlow-Vdd cannot.

Illustrative applications of how well bias can be modified duringvoltage-based testing, and related illustrative examples of defects thatcan be better detected with each application will now be discussed

Application 1: Decreasing Transistor Threshold Voltage

Decreasing a transistor's Vt can enhance the detectability of somedefects. Note that the following examples illustrate how defectdetectability can be enhanced by making the transistors stronger ratherthan weaker during test, as is done in the well-known low-Vdd testtechnique referenced above.

EXAMPLE 1 Dynamic Node Leakages

If there is a high-resistance short type defect between a dynamicfloating node and a signal line connected to the drain of an activen-transistor 16 (FIG. 1), the discharge of the node will be stronglyaffected by the RC constant determined by the equivalent resistance ofn-transistor 16 and the capacitance on the dynamic node. Increasing Vtwill decrease the equivalent resistance of n-transistor 16 and thereforemake the discharge faster and, therefore, easier to detect. Note thatincreasing Vdd would similarly decrease the equivalent resistance ofn-transistor 16, but would present a higher charge Q to be discharged inthe first place (charge Q=capacitance C times Vdd), which makesdetection harder.

EXAMPLE 2 Open Transistor Gate

Open transistor gates can cause delay faults in circuits. For example,when using an open n-transistor gate in an invertor: when the inverterinput is low, the p-transistor turns on while the n-transistor gatecouples to its drain and turns on as a weak load. In that test condition(input driven low), detection is enhanced by the Vtn being decreased.With a decreased Vtn, n-transistor 16 presents a stronger load (lowerequivalent resistance), which reduces the inverter output and makes thedegraded high output easier to detect. Note that increasing Vdd wouldalso make n-transistor 16 present a stronger load, but also makesp-transistor 20 stronger, which makes detection more difficult. Notealso for this example that it is useful to be able to control Vtn andVtp independently. In this case, making n-transistor 16 load strongerwithout making p-transistor 20 stronger enhances defect detection.

Application 2: Independently Changing Vtn and Vtp

Independently changing Vtn and Vtp can enhance detection of defects insome circuits by changing voltages on defective nodes, changing logicgate thresholds, and changing critical path composition.

EXAMPLE 1

Independently changing Vtn and Vtp can uniquely detect some circuitswith defects by changing the voltage on the defective node. For example,one may have a signal-to-signal resistive short defect between a largep-transistor and a small n-transistor, where the only observation pointis at the drain of the p-transistor. In this case decreasing Vtn but notVtp, reduces the voltage on the observed node from above the drivengate's logic threshold to below it, allowing for observation of thedefect since an incorrect (low) voltage must be observed at that nodefor detection. Decreasing Vtn but not Vtp could be accomplished byincreasing p-well 14 bias, but leaving n-well 18 bias at its nominalvalue. Detection would be further enhanced by increasing Vtp to reducethe voltage on the observed node even further due to an even better(higher) strength ratio between the n-transistor and p-transistor.Increasing Vtp could be accomplished by increasing n-well 18 bias from anominal value. Such a defect could similarly be detected by decreasingVtn and/or increasing Vtp and then applying a voltage-based timing test(i.e., a voltage test run at a speed close to maximum for the IC), inwhich case there would be a less restrictive requirement on the degradednode's voltage.

EXAMPLE 2

Modifying one well bias to increase or decrease a respective Vt, but notthe other well bias, or increasing a respective Vt while decreasing theother, changes the logic threshold of gates in the circuit Modifyingboth well biases/Vts together can also change logic thresholds, butmodifying each independently can be used to achieve a much more dramaticeffect. Defects (especially difficult-to-detect ones) generally causedegraded logic levels. Changing the logic thresholds, the gate or gatesdriven by a degraded logic level could cause a circuit to go frompassing to failing, or vice versa. Changing VDD also changes logic gatethresholds, but modifying Vtn and Vtp separately gives a great deal ofcontrol. For example, consider a floating node whose voltage isdetermined by capacitive coupling to VDD and GND. Independentlymodifying Vtn and Vtp can make the logic level seen by the driven gatego from ‘1’ to ‘0’, and vice versa.

EXAMPLE 3

Modifying Vtn and Vtp will change the critical Paths of the circuit andthereby enhance detection of timing defects. Timing defects allow thecircuit to function correctly at slow speeds, but cause the circuit tofail when it is run at fast speeds, e.g., speeds at or close to therated speed. This is especially the case when Vtn and Vtp are modifiedindependently. For example, delay tests are in general hampered by thefact that long paths can hide timing defects in short paths. ModifyingVtn and/or Vtp changes the relative lengths of paths. Individual controlof the transistor thresholds provides great flexibility for lengtheningnominally short paths and shortening nominally long paths such thattiming defect coverage is enhanced without additional patterns.

In one embodiment, the method as applied to Application 2 may beimplemented by using well bias modification to modify threshold voltagesVts to: (a) strengthen p-transistor 20 and weaken n-transistor 16 bydecreasing the p-well 14 bias for n-transistor 16 and decreasing n-well18 bias for p-transistor 20; (b) strengthen n-transistor 16 and weakenp-transistor 20 by increasing p-well 18 bias for n-transistor 16 andincreasing n-well 18 bias for p-transistor 20; or (c) strengthen bothtransistors by increasing p-well 14 bias for n-transistor 16 anddecreasing n-well 18 bias for p-transistor 20. The determination ofdefects can occur with any setting above.

More complex testing regimens may also be implemented. For example, thefollowing regimen may be implemented: first setting each well bias at anominal value; second increasing p-well 14 bias from a nominal value andsetting n-well 18 bias at a nominal value; and third setting p-well 14bias at a nominal value and decreasing n-well 18 bias from a nominalvalue. The determining step would occur between each of the above steps.The above-described regimen may further include: fourth setting p-well14 bias to a lower than nominal value and n-well 18 bias to a higherthan nominal value; fifth setting p-well 14 bias to a lower than nominalvalue and n-well 18 bias to a lower than nominal value; and sixthsetting p-well 14 bias to a higher than nominal value and n-well 18 biasto a higher than nominal value. Again, the determining step would occurbetween each of the above steps. It should be recognized that othercombinations of n-well and p-well biases could also be used. A searchcould also be done for the minimum and/or maximum of each well bias atwhich the chips will still operate. The n-transistor and p-transistorsearches could be done together or independently. The minimum or maximumwell bias could be compared to circuit parameters such as the chipminimum/maximum operating VDD or IC speed as determined by, for example,a ring oscillator, i.e., a set of circuits with an odd number ofinversions used to monitor IC speed, or by measuring a maximum frequency(Fmax) at which the IC will function.

Application 3: Simultaneously Modifying Well Bias And Other ControllableCircuit Parameters

EXAMPLE 1

Some defects can be uniquely detected by simultaneously modifying VDDand Vt together. For example, some cross talk is best detected with highVDD (large crosstalk) and low Vt (low noise margins).

EXAMPLE 2

Characterizing VDD versus well bias behavior for a circuit may detectunique problems such as the crosstalk example above, and also may helpto distinguish between defects (i.e., test-based failure analysis). Asused herein, “characterization” means comparing of two parameters insuch a way as to discern differences.

EXAMPLE 3

Applying a low-VDD test and Vt modification at the same time can alsoprovide advantages. For example, circuits that are weakened (andtherefore made more sensitive to defects) by low-VDD can be furtherweakened (and therefore made more sensitive) by increasing Vt. If thecircuit cannot tolerate weakening by increasing both Vtn and Vtp, it maytolerate weakening just one, which will enhance detection. In this case,a low-VDD test and Vt modification can aid test resolution, which isnormally limited because minimum VDD for a circuit is limited by theweakest block. In other cases, circuits might not be able to functionwith the transistors any weaker than that provided during the low-VDDtest, in which case the techniques that decrease Vtn and/or Vtp (i.e.,strengthen the transistors) combined with the low-VDD test areespecially valuable. In particular, circuits can be weakened by low-VDDand then a modified well bias used to change parameters such asdefect-related degraded circuit voltages and logic gate thresholds, asdescribed above. The defect-detection effect of the latter modificationswill be enhanced by the circuit's low-VDD weakened state. In someinstances, characterizing minimum VDD versus maximum well bias can aidachieving process insensitivity in test results.

Application 4: Characterizing Well Bias Behavior Versus Other ObservableCircuit Parameters

Comparison tests can also be applied. For example, at least one extremecondition setting for a well bias can be tested and defects determined.For example, one of a minimum or maximum well bias attainable versus aspeed at which the IC will function may be used to detect defects. Inthis case, the minimum and/or maximum well bias at which the ICfunctions at a particular speed can be determined, and then compared toa predetermined goal. The “goal” can include a value for the minimumand/or maximum well bias attainable. Again, IC speed may be measured byring oscillators, or by measuring a maximum frequency (Fmax) at whichthe IC will function. Similar to the minimum VDD, the maximum well biasat which the circuit works should depend on things that also affect ICspeed. Using well bias modification during test gives a new independentdimension (i.e., a new “lever”) for these comparison tests.

Application 5: Using a Chip's Own Well Bias Behavior as a Reference

The chip under test can act as its own reference during test anddiagnosis. That is, the circuit's output for a certain test can becompared to a reference output of the same circuit under different wellbias conditions. On a good chip, changing Vts a small amount should notchange the test results, e.g., the logic values observed at scan chainlatches or primary outputs 70, 72 (FIG. 1) should not change. On adefective chip, the logic values may change as a result of phenomenasuch as changing logic gate thresholds or changing values of degradedvoltages, etc., as described above. In this case, the chip can be usedas its own reference by comparing the test results obtained with thetest run under one set of well bias conditions to those obtained withthe test run at a different set of well bias conditions. Accordingly, apredetermined set of expectation data for comparison is no longerrequired.

Application 6: Bump or Retention Testing

EXAMPLE

Bump or retention type testing using well bias as the weakeningmechanism. This technique can be advantageous for random access memory(RAM) retention testing, e.g., a cell with a missing p-transistor willeventually flip to its preferred state. Threshold voltage (well bias)modification can be used to make the flip happen faster, therebydecreasing the time required for retention testing. In the case of“bump” testing, the testing step may include stimulating the circuitwith a test vector, as discussed above, followed by the step ofmodifying the well biases for a predetermined time. Determination of adefect then includes observing the test vector.

Application 7: Separate Well Partitions

Referring to FIG. 2, separate well partitions (e.g., n-well ispartitioned and/or p-well is partitioned) provide additional advantagesfor test and diagnosis. Testing may include applying a different wellbias to at least one partition compared to at least one other partition.The determination of a defect may then be applied to the circuit as awhole or on a partition-by-partition basis. For example, any of thetests outlined in the Applications or EXAMPLES above may be applied on apartition-by-partition basis. In another example, adifferential-extreme-operating-well-bias scheme may be applied frompartition-to-partition. Additional variables may be provided forcritical path modification and changing logic thresholds, if paths crosswell bias boundaries. In terms of overall advantages, the requirementsthat the whole circuit work at certain conditions, e.g., well biasconditions, the same VDD, etc., may be relaxed using partitions.Further, test resolution provided by being able to test each partitionagainst its own expected tolerable modified-Vt conditions may beenhanced. Diagnosis achieved by modifying Vt in different partitionsindependently, including localizing to a partition or, if paths crosspartition boundaries, localizing to a path segment possibly using“chip-as-its-own-reference” diagnosis techniques, may also be provided.

Another advantage of well bias modification during voltage-based testingis that test techniques that decrease Vt do not require a reduced testspeed as do such methods as decreased VDD.

The above described voltage-based testing using well bias modificationmay be implemented using various structural features.

First, well bias modification may be implemented by controlling the biasof the bulk during testing using control unit 40. For cases where thereis only a single electrically connected n-well and a single electricallyconnected p-well, control mechanisms can be implemented. For example,binary control at test for whether the substrate is at the circuit VDD(GND) or a modified VDD (GND) may be implemented. In this case, optionsinclude, for example: a direct pin-out control signal, or a test padavailable only at the wafer test or via a register bit under scan chaincontrol. Alternatively, control (at least binary) of the n-substrate andp-substrate independently may be implemented. Control allowing bothincreases and decreases in the substrate voltages versus nominal voltagemay be implemented. Full analog control of the well bias voltage mayalso be provided by, for example, a direct pin-out, a test pad availableonly at the wafer test, or a control register under scan chain controlplus a digital-to-analog converter (DAC). The above control mechanismsmay be implemented independently of the chip, or as integrated biascontrol circuits as known in the art.

Second, where multiple well partitions are provided, separate biascontrol can be implemented for testing. A multiple well bias partitionmethodology would be natural where parts of the circuit are active whileother parts are idle. For some test and diagnosis methods describedabove, a design methodology where wells are partitioned, e.g. anapplication specific integrated circuit (ASIC) methodology wherewell-islands are geographically defined, may be advantageous.

The above-described applications of well bias modification duringvoltage-based testing make defects more detectable by decreasing(strengthening transistors) instead of increasing Vts (weakeningtransistors); independently controlling Vts for n-transistors separatelyfrom those for p-transistors; using relationships between Vt and minimumoperating VDD or other measurable or controllable circuit parameters fordefect detection and circuit characterization; taking advantage ofseparately-wired well partitions, if they exist; and using Vtmodification for enhancing diagnosis.

II. IDDQ Testing

A transistor's well bias has a strong effect on its threshold voltageVt, which in turn has a strong effect on its static leakage currentIDDQ. The methods described below provide both increases and decreasesin threshold Vt to exploit the relationship between well bias and IDDQrather than just using well bias to decrease IDDQ. In addition, themethods allow characterization of multiple independent relationships bymodifying Vtn and Vtp independently. In general, the methods rely onmeasuring IDDQ at two or more well bias conditions and comparing theinferred relationship between IDDQ and well bias to the relationshipexpected for a defect-free circuit. Compared with methods that compareIDDQ at different supply voltages VDD, well bias modification allows: awider range of IDDQ testing without damaging the device with largeelectric fields across the gate oxide, characterizing multipleindependent relationships by modifying Vtn and Vtp separately, andincreases the ability to induce jumps in IDDQ due to degraded logiclevels exceeding lowered transistor thresholds or falling belowincreased transistor thresholds.

Relative to IDDQ testing, the method may include the steps of: applyinga test vector, applying a first set of biases to n-well 18 and p-well 14(e.g., through control points 42, 44-FIG. 1), measuring the IDDQ,applying a different second set of biases to the wells, and measuringIDDQ again. The results of the IDDQ testing under the multiplicity ofwell bias conditions are then compared to expected results for adefect-free circuit to determine whether a defect exists. Note that thetest vector can be applied with the chip under either nominal ormodified well bias conditions. It can optionally be applied andre-applied prior to setting the desired well biases and measuring theIDDQ. The steps of modifying well bias-measuring IDDQ can be repeatedfor different test vectors. What is determined to be “expected results”may be generated by empirical analysis of a number of tests for manychips. The application and measuring steps may be repeated a number oftimes prior to the comparison. There are a number of ways of comparingthe results to determine whether a defect exists using modified wellbias IDDQ testing.

A. Relationships Comparison

In one embodiment, defects can be detected by comparing generalrelationships between IDDQ of a defect-free circuit and that of adefective circuit using well bias modification. For example, adifference, i.e., a “delta,” in IDDQ when the well bias is modified canbe detected when a degraded voltage on a node moves from being below thedriven transistor's Vt to above it. In another example, IDDQ may includeone or more large changes or “jumps” in value as the well bias variessmoothly, indicating a defect.

EXAMPLE

A defect exists in the form of an unintentionally open node. The voltageof the open node is determined by the voltages' on a neighboring wire.Assume that the neighboring wire always happens to be at the correctvoltage for the open node during the test such that the open nodevoltage is on the correct side of the logic threshold of the drivengate, but is degraded. Assuming the open node is at a degraded logic 0,as long as the degraded voltage 0 has a voltage less than Vtn in thedriven gate, there will be no defect-related IDDQ. However, if Vtn isdecreased to a value below the voltage on the degraded node during thetest, there will be a jump in IDDQ. In contrast, in a defect-free chip,the node on which the unintentional open node occurs in the circuit willhave a value of approximately 0 V, i.e., less than the decreased Vtn. Inthat case, there will be no similar jump in IDDQ. Accordingly, thedefect is more easily detected.

With further regard to the above EXAMPLE, note that in contrast toturning on IDDQ by decreasing a Vt, turning off IDDQ by increasing athreshold voltage Vt can also lead to a jump in IDDQ that would beabsent for a defect-free chip. For example, the degraded voltages at theends of a resistive signal-line-to-signal-line bridge can cause “fan-outcurrent” in the driven gates. Such fan-out current could be turned offby increasing one or more transistor thresholds Vt in the driven gates,causing an unexpected decrease in the IDDQ. In a defect-free circuit,there would be no fan-out current and therefore no similar decrease inIDDQ. Accordingly, the defect is more easily detected.

B. Curve Shape Comparison

In another embodiment, the process may implement an IDDQ curve shape orgraphical comparison by: establishing an IDDQ curve shape(s) for adefect-free circuit (e.g., with a point-by-point model or modeling thecurves as linear or exponentials) and an IDDQ curve shape for a circuitunder test, and comparing the IDDQ curve shapes. Establishing an IDDQcurve shape for a defect-free circuit may include measuring IDDQ atdifferent sets of well biases for many chips. Similarly, establishingthe IDDQ curve shape for the circuit under test may also includemeasuring IDDQ at different sets of well biases.

FIGS. 3-4 illustrate the benefits of this technique. In this case,different p-well biases were applied to a circuit and the resulting IDDQwas measured. The circuit used to build the illustration was a standardcell inverter with a resistor modeling a short from the output to VDD.Of course, the technique can be applied to any circuit. From themeasurements, a graphical representation is generated as shown in FIG.3. In FIG. 3, the p-well 18 bias is presented in milli-Volts (mV) alongthe horizontal axis, and the IDDQ is presented in milli-Amperes (mA)along the vertical axis. The dotted curves, i.e., lines, show theresults for defect resistances of 1 ohm (top dashed line), 1 Kohm(middle dashed line), and 10 Kohms (bottom dashed line). The solid curverepresents the same relationship for a defect-free static leakagecurrent IDDQ. Note that the defect-related IDDQ curves have flat shapes,which makes them easy to distinguish from the exponential shape of adefect-free IDDQ curve. The 10 Kohm curve is almost entirely flatbecause the IDDQ in the sample circuit is determined by the defectresistance. Regardless of the well bias, there is approximately VDDacross the defect resistance, so the current is independent of the wellbias. In the 1 ohm case, the IDDQ is limited by the transistor, so thecurve shown reflects the dependence of the transistor's saturationcurrent on the well bias. While the well bias does have an effect ondrain saturation current (IDsat), i.e., theoretically approximatelyquadratic, the shape of the defect curves are still easily distinguishedfrom the exponential defect-free IDDQ curve.

For comparison, FIG. 4 shows a prior art graph illustrating thedifficulties of detecting defects using the relationship between IDDQand VDD for the same circuit. In this graph, IDDQ is presented inmilli-Amperes (mA) along the vertical axis, and VDD is presented involts (V) along the horizontal axis. Again, dashed lines represent acircuit with a defect, and solid lines represent a defect-free IDDQcurve. In this example, the defect-free IDDQ curve is varied overapproximately the same range as in FIG. 3. However, in this case, thedefect-related IDDQ curves have shapes much closer to the defect-freeIDDQ curve. Accordingly, more easily distinguished curve shapes aregenerated by modifying the well bias (FIG. 3) compared to an IDDQ versusVDD technique (FIG. 4).

C. Outlier Rejection Techniques

Another embodiment may include performing testing some number npre-determined well bias settings, and use n-dimensional outlierrejection techniques to identify defective circuits. Outlier rejectiontechniques function to locate samples that do not fit the native, i.e.,defect-free, distribution.

With regard to the comparison embodiments above, the separate wiring ofn-well 18 and p-well 16 allows the well bias and hence the Vtn(s) andVtp(s) to be adjusted independently. This ability can be beneficial, forexample, because it can provide two different characteristicrelationships to compare against. This would be especially helpful inthe case where IDDQ versus well bias characteristics is quite differentbetween n-transistors and p-transistors. For example, where onetransistor's results are more representative of a defective circuitrelationship than the other. Separate wiring also allows changing of thecircuit state by modifying logic thresholds without changing any otherinputs.

Well bias modification can also be used to effectively turn off, or atleast substantially decrease, one type of IDDQ, i.e., n or p, and thenperform a variety of characterizations on the other type versus at leastone circuit parameter. Such characterization might include currentversus voltage, current versus temperature analysis, or current versuswell bias. It could also include comparing IDDQ using one test vectorversus another. Characterizing one type at a time can be expected toprovide a much more uniform relationship for each element beingcharacterized and therefore a stronger and easier to understand set ofstandard relationships. Such techniques could also be used to learnabout the composition of the leakage current.

In another embodiment, the well-bias modification may be used as anotherindependent variable in multi-parameter testing (e.g., IDDQ versuswell-bias versus IC speed (as measured by a ring oscillator). It canalso be used in characterizing IDDQ to learn about its origin. Forexample, defect-related IDDQ that flows through n-transistors can bedistinguished from defect-related IDDQ that flows through p-transistorsby strengthening only n-transistors at once and observing whichmodification affects defect-related IDDQ.

III. Stress Testing

Well bias modification also provides an alternative way to stress a chipand find latent defects for certain classes of circuits. For example,well bias modification allows generation of large currents for stressinga chip without application of a high and damaging electric field acrossthe gate oxide and without necessarily relying on high temperature,i.e., without necessarily requiring a burn-in oven. In addition, becausethe transistor threshold voltage (Vt) has a strong effect on bothswitching and static transistor currents, the method allows tuning thewell biases during stress to achieve the desired mix of static andswitching currents. Accordingly, it provides a method for improvedcircuit stress compared to standard voltage stress and burn-in stresstechniques. In addition, the method also helps circuits function atstress conditions and allows for localizing and diagnosing defects. Themethods can be used to “bump” gate oxide stress and tailor well bias ona chip-by-chip basis during burn-in. As with voltage-based testing andIDDQ testing, partitions are also beneficial relative to stress testing.

Application 1: Current Control

Transistor switching currents are strongly dependent on thresholdvoltage Vt based on the well-known simplified equationI_(DSsat)=K*W/2L(Vgs−Vt)ˆ2, where K is the transistor transconductanceparameter, W is the transistor width, L is the transistor length, Vgs isthe voltage difference between the transistor's gate and source nodes,and Vt is the transistor threshold voltage. In particular, modifyingwell bias modifies Vt and therefore modifies switching currents. Asdescribed above, an aim of stressing chips is to generate largeswitching currents. Modifying well bias uses Vt decreases during stressto achieve that goal. Using low Vt instead of high VDD creates highcurrents without putting a high and damaging electric field across thegate oxide. In addition, using low Vt to generate the current could helpavoid false defects due to crosstalk which is more severe under voltagestress elevated VDD than it is under nominal VDD. Modifying well biasesto modify switching currents can be done: (1) as a stress mechanismitself in the absence of elevated temperature or voltage, (2) duringvoltage-based stressing, or (3) during burn-in stressing, where “burn-instressing” usually connotes high-temperature stressing and sometimeshigh temperature and high voltage stressing.

Transistor subthreshold leakage currents are also strongly sensitive toVt, according to the simplified equation,I_(DSsub)W/L*I_(d0)*eˆ(Vgs−Vt)/nV′, where W is the transistor width, Lis the transistor length, I_(d0) is a process parameter related to thetransistor transconductance and is independent of Vt, Vgs is the voltagedifference between the transistor's gate and source nodes, Vt is thetransistor threshold voltage, n is a constant process parametertypically around 2, and V′ equals kT/q in which k is Boltzmann'sconstant, T is temperature in Kelvin and q is the charge of an electron.In particular, increasing Vt decreases static leakage current IDDQ. Asdescribed above, another important element of stressing chips is tocontrol the power drawn. Modifying well biases uses Vt increases todecrease subthreshold leakage during stress to achieve that goal.

Finally, design compromises are often required to get circuits to workunder stress (elevated voltage and/or temperature) conditions. Modifyingwell biases allows using Vt modification during stress to aid circuitsin working under burn-in conditions.

Well bias modification can be applied on the tester or in the burn-inoven. In addition, it can be used as the sole stress mechanism or incombination with elevated voltage and/or temperature. The choice dependson the target defects to be accelerated. Further, where a burn-in ovenis in use, many circuits may be stressed at once, and the current drawnand temperature of each circuit can be monitored individually. Inaddition, the well biases can be set individually.

Well bias modification during stress testing can be used as a simple orsophisticated control mechanism for switching current or static currentduring on-the-tester stress or during burn-in. Examples of simplecurrent controls include: always decreasing transistor Vts duringvoltage-based stressing to enlarge switching currents; or alwaysincreasing transistor Vts during burn-in stressing to decrease thestatic leakage currents.

More sophisticated current controls may include:

EXAMPLE 1 Tailoring Well-bias Control on Chip-by-Chip Basis

Threshold voltage Vt can be adjusted in the burn-in oven to obtain thedesired amount of switching current without unnecessary static leakagecurrent. To implement this strategy, the switching currents drawn by achip during burn-in would be monitored and Vt adjusted such that thechip draws a predetermined desired amount of switching current thatwould in most cases be the same for each chip. Short channel chips wouldnaturally draw large switching current and therefore allow a higher Vtsetting than longer channel chips. The relatively high Vt setting wouldcontrol the static leakage current, which also would be expected to behigher on the shorter channel chips. Long channel chips, on the otherhand, would require setting Vt lower. The current measurement and Vtcontrol signal generation could be done within the burn-in tester.

Because chip temperature is strongly determined by static and switchingcurrents, which in turn are strongly dependent on well bias through itseffect on Vt, well bias can also be used to control temperature. Forexample, the temperature of each chip could be monitored, e.g., via asensor external to the chip 50 (FIG. 1) or an on-chip sensor 52 (FIG. 1)like a thermistor, and the well bias(es) controlled by control unit 40(FIG. 1) to maintain a desired stress test temperature. Decreasing VDDwould achieve a similar current-limiting effect. Using Vt adjustment,however, provides two advantages. First, unlike VDD, threshold voltageVt itself provides no stress. Accordingly, there is nodefect-acceleration loss associated with increasing Vt. Second,increasing Vt has a strong effect on both switching and subthresholdleakage currents. VDD, on the other hand, has a strong effect on onlyswitching currents. VDD's effect on subthreshold leakage current IDDQ isrelatively weak, being only through the Drain Induced Barrier Lowering(DIBL) effect.

EXAMPLE 2 Switching Well Bias

Switching the well bias during burn-in or voltage stress so that the Vtsare low when the circuit switches and high when circuit does not switchprovides high peak switching currents as a stress mechanism whilelimiting static leakage. This process may include, for example,increasing p-well 14 (FIG. 1) bias and decreasing n-well 18 bias whencircuit switching is to occur; and decreasing p-well 14 bias andincreasing n-well 18 bias when circuit switching is not to occur.Limiting the static leakage current diminishes the power requirementsand helps prevent chip temperature rise and thermal runaway. Switchingwell bias during burn-in could be done by synchronizing the Vt voltagewith the clock.

EXAMPLE 3 Setting Vt Differently During High Voltage Burn-in VersusNominal Voltage Burn-In

Where a high voltage stress is desired but not required for the entirelength of the burn-in, leakage current could be controlled during anelevated voltage portion of the burn-in by setting Vt high. Thereafter,generation of large switching currents during a non-elevated-voltageportion of the burn-in (by setting Vt low) could occur.

Application 2: Aid Circuit Functionality During Burn-In

Well bias modification to control Vt can also be used to help circuitsto function under burn-in operating conditions. One reason circuits failto function at elevated VDD during burn-in is that path delay becomesmore RC dominated than it is at nominal VDD. The change occurs becausethe transistors speed up, but the interconnect does not. That change inpath delay composition may lead to the violation of critical raceconditions. For example, to prevent violation of a latch hold time, datamust not arrive at the latch input until a specified amount of timeafter the clock arrives at the clock input. If the data path isgate-delay-dominated, while the clock distribution network iswire-delay-dominated, the hold time may be violated under elevated-VDDconditions due to speeding up of the data path relative to the clockdistribution path. Under nominal conditions, there may not be a holdtime violation. Ideally the circuit would not need to be timed to workat out-of-spec VDDs. To relax that requirement, Vt could be increasedwhen the circuit is run at elevated VDD. The increase in Vt wouldcounter the transistor speed-up, have no effect on the interconnectdelay and, therefore, keep the path delay composition closer to thatappearing under nominal circuit operating conditions.

Another reason circuits might not function at burn-in conditions is thathigh temperatures cause increased leakage currents, which may causedynamic nodes to lose their charge too quickly and therefore cause thecircuit to fail. To avoid design concessions to eliminate the problem,one could increase Vt during burn-in, which would decrease the leakagecurrents and therefore counter the high-temperature effect. Similarly,high temperature conditions lead to problems with VDD droop because ofthe increase resistivity of the metal power grid. Lowering switchingcurrents by increasing Vts during all, or part, of burn-in mitigates theVDD droop and prevents designers from having to accommodate VDD droopduring burn-in.

EXAMPLE

Independent control of Vtn and Vtp may be exploited to find operatingconditions where the circuit can function. For example, to help dynamicnodes maintain charge, only Vtn may be increased, while Vtp remains at anominal value.

Application 3: Partitions

As noted above relative to IDDQ testing, circuits with wells wiredseparately from circuit VDD and GND may have just a single shared p-wellnode and a single shared n-well node, or the p-well and n-well nodes maythemselves be partitioned. If the wells are partitioned, as shown inFIG. 2, stress conditions can be controlled on a partition-by-partitionbasis, which can be useful for such things as relaxing the constraintthat all partitions of the circuit must be able to function under thesame stress conditions. In addition, the Vt-induced high-current stresscan be applied to only part of the circuit at a time to minimize thepower requirement. Even if the wells are not partitioned, n-transistorand p-transistor Vt can be lowered one at a time to minimize stress fromthe power requirement.

Partitioned wells can also aid with defect localization. Specifically,“temporary” stress defects, i.e., those that cause circuit malfunctiononly under stress and not under normal operational conditions, can belocalized to a partition. The localization may be done by repeatedlyrunning the stress test with just one or a subset of the partitionsseeing the stressful well bias conditions. The partition containing thedefect can be identified as the one whose being in the stressfulcondition causes the failure, i.e., test failure or circuit malfunction.If this process is completed methodically during test, stress-relatedpermanent defects could also be localized to a partition. Assuming thepartitions cannot be tested independently, such a localization wouldrequire serially stressing each partition and checking for a defect. Thelocalization could not be done in a post-processing step because oncethe stress defect becomes permanent, the defect would be present nomatter which partition is put into the stress condition.

If paths cross well bias partitions, the fail site can be furtherlocalized to a sub-path within one partition. In addition, even if thewells are not partitioned, temporary defects where the current flowsthrough n-transistors can be distinguished from temporary defects wherethe power flows through p-transistors by decreasing only Vtn or Vtp oneat a time. Controlling Vt during stress can also help with defectcharacterization, or “test-based-failure-analysis.” Specifically,problems sensitive to high currents can be distinguished from those dueto high fields by testing at both increased VDD and decreased Vt.

Application 4: High Electric Field Gate Oxide Stress

To accelerate some defects, e.g., gate oxide defects, to failure, it maybe desirable to put an elevated electric field across the gate oxide forsome portion of the circuit stress. For n-transistors whose p-well 14voltages are nominally at GND potential, lowering the p-well voltageprovides such an increased electric field. The same is true forp-transistors with the polarities reversed. Note that using well biasmodification to achieve the elevated electric field has the advantageover increasing VDD to achieve the elevated field because it is muchquicker to apply. Specifically, changing the power supply voltage VDD isa slower operation than changing the well-bias voltage. Also, whereasincreasing VDD causes the circuit to draw greater static leakagecurrent, well bias modification decreases the static leakage currentdrawn and, therefore, the static power consumed during gate oxidestress. In one embodiment, the well-bias would be bumped to the stresssetting in synchronization with the clocking of the circuit. Forexample, well biases would be set to nominal conditions just prior tothe clock switching and then set to the stress biases just after theclock switches for the remainder of the (probably lengthened versusnominal) clock period. Providing these steps would maintain nominalconditions during circuit switching, which would avoid the requirementfor the circuit to operate correctly under the stress conditions. Notethat a similar bump type stress would be much less practical with a VDDmodification instead of a Vt modification strategy because, as notedabove, changing the power supply voltage VDD is a much slower operationthan changing the well bias.

The above-described application of well bias modification during stresstesting controls static leakage during burn-in, but also takes advantageof being able to control dynamic switching current, not just staticcurrent. Moreover, the technique involves increasing that current as astress mechanism in itself. Selective control of both static and dynamiccurrent during the same circuit stress is also advantageous. Instead ofjust using the well bias as a blanket method for decreasing power duringburn-in, adjusting conditions to both optimally stress the circuit andcontrol power at once is advantageous. The technique can be tailored ona chip-by-chip basis during burn-in and also provides an alternativemeans for gate oxide stress. This technique also has extensions in termsof diagnosis and circuit functionality during burn-in.

IV. Miscellany

It should be recognized that while the methods have been describedrelative to particular steps that not all steps form the invention asoutlined in the attached claims. In addition, in many cases, theparticular order of steps disclosed can be changed without departingfrom the scope of the invention.

In the previous discussion, it will be understood that the method stepsdiscussed may be performed by a processor, such as CPU of control unit40, executing instructions of program product stored in memory. It isunderstood that the various devices, modules, mechanisms and systemsdescribed herein may be realized in hardware, software, or a combinationof hardware and software, and may be compartmentalized other than asshown. They may be implemented by any type of computer system or otherapparatus adapted for carrying out the methods described herein. Atypical combination of hardware and software could be a general-purposecomputer system with a computer program that, when loaded and executed,controls the computer system such that it carries out the methodsdescribed herein. Alternatively, a specific use computer, containingspecialized hardware for carrying out one or more of the functionaltasks of the invention could be utilized. The present invention can alsobe embedded in a computer program product, which comprises all thefeatures enabling the implementation of the methods and functionsdescribed herein, and which—when loaded in a computer system—is able tocarry out these methods and functions. Computer program, softwareprogram, program, program product, or software, in the present contextmean any expression, in any language, code or notation, of a set ofinstructions intended to cause a system having an information processingcapability to perform a particular function either directly or after thefollowing: (a) conversion to another language, code or notation; and/or(b) reproduction in a different material form.

While this invention has been described in conjunction with the specificembodiments outlined above, it is evident that many alternatives,modifications and variations will be apparent to those skilled in theart. Accordingly, the embodiments of the invention as set forth aboveare intended to be illustrative, not limiting. Various changes may bemade without departing from the spirit and scope of the invention asdefined in the following claims.

INDUSTRIAL APPLICABILITY

The invention is useful for testing integrated circuits.

1. A method for testing an integrated circuit (10) having wells (14, 18)that are wired separately from circuit VDD and ground, the methodcomprising the steps of: testing a circuit including independentlymodifying a p-well (14) bias of an n-transistor (16) and an n-well bias(18) of a p-transistor (20); and determining whether a defect existsfrom the testing.
 2. The method of claim 1, wherein the wells (14, 18)include partitions, the modifying step includes applying a differentwell bias condition to at least one partition compared to at least oneother partition, and the determining step is applied to one of thecircuit as a whole and on a partition-by-partition basis.
 3. The methodof claim 1, wherein the wells (14, 18) include partitions, the modifyingstep includes applying a plurality of different well bias conditions toa plurality of different partitions, and the determining step includescomparing the results of the testing to one another to localize adefect.
 4. The method of claim 1, wherein the testing step furtherincludes stimulating the circuit with a test vector followed by the stepof modifying the well biases for a predetermined time prior to thedetermining step.
 5. The method of claim 1, wherein the determining stepincludes comparing outputs of the circuit to expected results for adefect-free circuit.
 6. The method of claim 1, wherein the determiningstep includes comparing outputs of the circuit to results for the samecircuit under different well bias conditions.
 7. The method of claim 1,wherein the testing includes modifying the well biases to one of aplurality of extreme conditions.
 8. The method of claim 6, wherein thedetermining step includes observing a circuit parameter in addition towell bias during the testing.
 9. The method of claim 6, wherein thetesting step further includes modifying at least one circuit parameterother than well bias.
 10. The method of claim 1, wherein the testingstep further includes voltage-based testing.
 11. The method of claim 10,wherein the modifying step includes one of: (a) decreasing a p-well (14)bias for the n-transistor (16) and decreasing an n-well (18) bias forthe p-transistor (20); (b) increasing the p-well bias for then-transistor and increasing the n-well bias for the p-transistor; and(c) increasing the p-well bias for the n-transistor and decreasing then-well bias for the p-transistor.
 12. The method of claim 10, whereinthe voltage-based testing includes applying a low-VDD.
 13. The method ofclaim 10, wherein the modifying step includes: first setting each wellbias at a nominal value; second increasing the p-well (14) bias of then-transistor (16) from a nominal value and setting the n-well (18) biasof the p-transistor (20) at a nominal value; and third setting thep-well bias of the n-transistor at a nominal value and decreasing then-well bias of the p-transistor from a nominal value, wherein thedetermining step occurs between each of the above steps.
 14. The methodof claim 13, wherein the modifying step further includes: fourth settingthe p-well (14) bias of the n-transistor (16) to a lower than nominalvalue and the n-well (18) bias of the p-transistor (20) to a higher thannominal value; fifth setting the p-well bias of the n-transistor to alower than nominal value and the n-well bias of the p-transistor to alower than nominal value; sixth setting the p-well bias of then-transistor to a higher than nominal value and the n-well bias of thep-transistor to a higher than nominal value, wherein the determiningstep occurs between each of the above steps.
 15. The method of claim 10,wherein the determining step includes determining at least one of aminimum well bias and a maximum well bias at which the IC (10) functionsat a particular speed; and determining whether at least one minimum andmaximum well bias meets a predetermined goal.
 16. The method of claim 1,wherein the testing includes measuring an elevated static leakagecurrent (IDDQ).
 17. The method of claim 16, wherein the modifying stepincludes applying both increases and decreases of well bias to establisha relationship between IDDQ and well bias.
 18. The method of claim 16,wherein the step of applying includes: applying a first set of biases tothe n-well (18) and the p-well (14), and then measuring IDDQ; andapplying a different second set of biases to the n-well and the p-well,and then measuring IDDQ.
 19. The method of claim 16, wherein thedetermining step includes comparing the results of the applying step toexpected results for a defect-free circuit.
 20. The method of claim 16,wherein the determining step includes: establishing an IDDQ curve shapefor a defect-free circuit from the applying steps; establishing an IDDQcurve shape for a circuit under test; and comparing the curve shapes.21. The method of claim 16, wherein the modifying step includes settinga well bias to at least substantially decrease one type of IDDQ, and thestep of determining includes performing a characterization of the othertype of IDDQ versus at least one circuit parameter.
 22. The method ofclaim 1, wherein the testing includes stress testing.
 23. The method ofclaim 22, wherein the modifying step includes modifying well bias tomodify switching current.
 24. The method of claim 22, wherein themodifying step includes modifying well bias to modify current during atleast one of burn-in stressing and high-voltage stressing.
 25. Themethod of claim 22, wherein the modifying step includes modifying wellbias to draw a predetermined amount of at least one of switching andstatic current.
 26. The method of claim 22, wherein the modifying stepincludes: increasing the p-well bias and decreasing the n-well bias whencircuit switching is to occur; and decreasing the p-well bias andincreasing the n-well bias when circuit switching is not to occur. 27.The method of claim 22, wherein the modifying step includes settingwell-bias at a first setting during high voltage burn-in and a secondsetting during nominal voltage burn-in.
 28. The method of claim 22,wherein the modifying step includes setting well-bias during burn-in tomaintain circuit functioning.
 29. The method of claim 22, wherein themodifying step includes setting well-bias to maintain a stress testtemperature.
 30. The method of claim 22, wherein the modifying stepincludes modifying well bias during stressing to accelerate defects byplacing an elevated electric field across a gate oxide of the circuit.31. A method for testing a semiconductor circuit (10) having wells (14,18) that are wired separately from circuit VDD and ground, the methodcomprising the steps of: testing the circuit for a defect by measuringstatic leakage current; and increasing and decreasing well biases of ann-transistor (16) and a p-transistor (20) to change respectivetransistor threshold voltages during testing.
 32. A system for testing asemiconductor circuit (10) having wells (14, 18) that are wiredseparately from circuit VDD and ground, the system comprising: means fortesting (60) the circuit including independently modifying a well biasof an n-transistor (16) and a well bias of a p-transistor (20); andmeans for determining (62) whether a defect exists from the testing. 33.The system of claim 32, further comprising a temperature sensor (50, 52)for monitoring a temperature of the IC, wherein the means for testing(60) modifies the well biases to maintain a stress test temperature.